Crystalline-on-insulator (COI) substrates, such as silicon-on-insulator (SOI) substrates, are garnering interest since they have lower parasitic capacitance due to isolation from the bulk silicon. This improves power consumption. Additionally, SOI applications are resistant to latchup due to complete isolation of n-wells and p-wells. There are also other advantages in using SOI substrates, which result in overall increased performance.
As indicated, SOI substrates improve power consumption. This is particularly important with high voltage transistors, such as lateral drain-diffused (LD) transistors. For example, LD transistors are widely employed in high voltage applications. The use of COI substrates with LD transistors would result in lower power consumption.
However, conventional LD transistors formed on bulk substrates are not compatible with SOI substrates. For example, conventional LD transistors result in drift regions being disconnected from the channel, rendering it inoperable.
From the foregoing discussion, it is desirable to provide LD transistors which are compatible with CMOS applications using SOI substrates. It is also desirable to provide high voltage transistors with improved RF/Analog performance.